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Chủ Nhật, ngày 15 tháng 5 năm 2011

What is PCI Express?

PCI (Peripheral Component Interconnect) Express is a scalable I/O (Input/Output) serial bus technology set to replace parallel PCI bus which came standard on motherboards manufactured from the early 1990s through 2004. In the latter part of 2004 PCI Express slots began appearing alongside standard slots, starting a gradual transition.
Intel first introduced PCI technology in 1991 to replace the ISA/EISA bus. It was later taken over by The PCI Special Interest Group (PCI-SIG) who revised the protocol in 1993. Although robust enough to last over a decade, total available bandwidth of just 133 MB/ps shared between slots meant that high demand devices quickly saturated resources. In 1997 this problem was partially alleviated by implementation of a separate AGP slot (Accelerated Graphics Port) with dedicated bandwidth. Other steps were also taken at the chip level along with integrated components, which helped to extend PCI's viability. However, with the advent of SATA, RAID, Gigabyte Ethernet and other high-demand devices, a new architecture was required.

Intel answered with PCI Express, or PCIe for short.
PCI Express has several advantages, not only to the user but to manufacturers. It can be implemented as a unifying I/O structure for desktops, mobiles, servers and workstations, and it's cheaper than PCI or AGP to implement at the board level. This keeps costs low for the consumer. It is also designed to be compatible with existing Operating Systems and PCI device drivers.
PCI Express is a point-to-point connection, meaning it does not share bandwidth but communicates directly with devices via a switch that directs data flow. It also allows for hot swapping or hot plugging and consumes less power than PCI.
However the most promising feature is that it is scalable meaning greater bandwidth can be achieved through adding "lanes," ostensibly future-proofing into the next decade.

The initial rollout of PCI-Express provides three consumer flavors: x1, x2, and x16. The number represents the number of lanes: x1 has 1 lane; x2 has 2 lanes, and so on. Each lane is bi-directional and consists of 4 pins. Lanes have a delivery transfer rate of 250 MB/ps in each direction for a total of 500 MB/ps, per lane.
PCIe Lanes Pins MB/ps Purpose
x1 1 4 500 MB/ps Device
x2 2 8 1000 MB/ps = 1 GB/ps Device
x16 16 64 8000 MB/ps = 8 GB/ps Graphics Card
The 16-lane (x16) slot replaces the AGP for PCIe graphics cards, while the x1 and x2 slots will be used for devices. As graphic demands increase, x32 and x64 slots will be realized, and future versions of PCIe are expected to drastically increase lane data rates.

PCI Express is not to be confused with PCI-X, used in the server market. PCI-X improves on standard PCI bus to deliver a maximum bandwidth of 1GB/ps. PCIe has been developed for the server market as well, initially with the x4, x8 and x12 formats reserved. This far exceeds PCI-X capability.  

Standard PCI is predicted to remain prevalent through 2006 while consumer-owned products and shelf-products filter through the market. Manufacturers of products that have high bandwidth requirements will logically be the first to take advantage of PCI Express capability with graphics cards leading the way.
PCIe slots are available on both Intel and AMD motherboards.


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